View M5M51R16AWG-10LI_406696.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
DESCRIPTION The M5M51R16AWG is a 1048576-bit CMOS static RAM organized as 65536 words by 16-bits, which are fabricated using high-performance CMOS technology. The use of CMOS cells and periphery results in a high density and low power static RAM. The M5M51R16AWG can achieve low stand-by current and low operation current and ideal for the battery back-up application. The M5M51R16AWG is packaged in a 48-pin chip scale package which is a high reliability and high density surface mount device (SMD). Using this type of devices, it becomes very easy to design a small system. The M5M51R16AWG is fully compatible with the M5M51R16WG.
PIN CONFIGURATION (TOP VIEW)
1 A
BC1
2
3
4
5
6
OE BC2
A6 A7 A5 NC
A3 A2 A1 A4 NC A14 A13 A12
A0 S DQ2 DQ4
NC DQ1 DQ3
B
DQ16
C
DQ14 DQ15
D
GND DQ13
VCC
E VCC F
DQ11 DQ10 A9 A10 A11 DQ7 W A15 DQ6 DQ8 NC DQ12 GND DQ5 GND
FEATURE Power supply current Type name M5M51R16AWG- 10LI M5M51R16AWG- 12LI M5M51R16AWG- 15LI M5M51R16AWG- 10HI M5M51R16AWG- 12HI M5M51R16AWG- 15HI Access time (max) 100ns 120ns 150ns 100ns 120ns 150ns Active (max) Stand-by (max) 4A 10mA (1MHz) 2A
G
DQ9 NC A8
H
NC
PIN CONFIGURATION (BOTTOM VIEW)
* Single +1.8V~2.7V power supply * Low power down current 0.05A(typ.) * Directly TTL compatible : All inputs and outputs * Easy memory expansion and power down by S,BC1 and BC2 * Data hold on +1.0V power supply * Three-state outputs : OR-tie capability * OE prevents data contention in the I/O bus * Common data I/O * Separate control of lower and upper bytes by BC1 and BC2 * Package 48-pin chip scale package(CSP) Ball pitch : 0.75mm Package size: 7.0mm x 8.5mm APPLICATION Small capacity memory units.
6 A
NC
5
4
3
2
1
A0 S DQ2 DQ4 DQ5 DQ7 W A15
A3 A2 A1 A4 NC A14 A13 A12
A6 A7 A5 NC GND A9 A10 A11
OE BC2
BC1 DQ16
B
DQ1
C
DQ3 DQ15 DQ14 DQ13 GND DQ12 VCC DQ10 DQ11 NC A8 DQ9 NC
D VCC E
GND
F
DQ6
G
DQ8
H
NC
Outline
48FJA
NC : NO CONNECTION
Aug.1. 1998
MITSUBISHI ELECTRIC
1
MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM FUNCTION The operation mode of the M5M51R16A series are determined by a combination of the device control inputs S, W, OE, BC1 and BC2. Each mode is summarized in the function table. A write cycle is executed whenever the low level W overlaps with the low level BC1 and/or BC2 and the low level S. The address must be set up before the write cycle and must be stable during the entire cycle. The data is latched into a cell on the trailing edge of W, BC1, BC2 or S, whichever occurs first, requiring the set-up and hold time relative to these edge to be maintained. The output enable input OE directly controls the output stage. Setting the OE at a high level, the output stage is in a high-impedance state, and the data bus contention problem in the write cycle is eliminated. A read cycle is executed by setting W at a high level and OE at a low level while BC1 and/or BC2 and S are in an active state. (BC1 and/or BC2=L, S=L) When setting BC1 at a high level and the other pins are in an active state, upper-Byte are in a selectable mode in which both reading and writing are enabled, and lower -Byte are in a non-selectable mode. And when setting BC2 at a high level and the other pins are in an active state, lower-Byte are in a selectable mode in which both reading and writing are enabled, and upper -Byte are in a non-selectable mode. When setting BC1 and BC2 at a high level or S at a high level, the chips are in a non-selectable mode in which both reading and writing are disabled. In this mode, the output stage is in a high-impedance state, allowing OR -tie with other chips and memory expansion by BC1, BC2 and S. S, BC1 and BC2 control the power down feature. When S, BC1 and BC2 go high, the power supply current is reduced as low as the stand-by current which is specified as Icc3 or Icc4, and the memory data can be held at +1.0V power supply, enabling battery back-up operation during power-failure or power-down operation in the non-selected mode. FUNCTION TABLE
S W OE BC1 BC2 LHL L L L L L L L L X H H H L L L L L X X X H L L H L X H X Mode Word Read Upper-Byte Read Lower-Byte Read
(Upper-Byte Non selection)
Icc DQ1~8 DQ9~16 Dout Active Dout Dout High-Z Din Din High-Z Active Active Active Active Active
L (Lower-Byte Non selection) High-Z H L L H X H X Dout Din High-Z Din
Word Write Upper-Byte Write
(Lower-Byte Non selection)
Lower-Byte Write
(Upper-Byte Non selection)
HH XX XX
Output disable Non selection Non selection
High-Z High-Z Active High-Z High-Z Stand-by High-Z High-Z Stand-by (High-Z=High-impedance)
BLOCK DIAGRAM
A4 D4 A3 A4 A2 B4 A1 C4 A0 A5 A15 H5 A14 F4 A13 G4 A12 H4 ADDRESS INPUTS 65536 WORDS x16 BITS ( 512 ROWS x 256 COLUMNS x 8 BLOCKS ) B6 DQ1 C5 DQ2 C6 DQ3 D5 DQ4 E5 DQ5 F6 DQ6 F5 DQ7 G6 DQ8 G1 DQ9 F2 DQ10 A8 H2 A9 F3 A10 G3 A11 H3 F1 DQ11 E2 DQ12 D2 DQ13 C1 DQ14 C2 DQ15 B1 DQ16 A7 B3 A5 C3 A6 A3 CLOCK GENERATOR CHIP SELECT S B5 INPUT WRITE CONTROL W G5 INPUT OUTPUT ENABLE OE A2 INPUT BYTE CONTROL INPUTS BC2 B2 BC1 A1 D6 Vcc E1 Vcc E6 GND (0V) D1 GND (0V) E3 GND (0V) DATA INPUTS/ OUTPUTS
Aug.1. 1998
MITSUBISHI ELECTRIC
2
MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
ABSOLUTE MAXIMUM RATINGS Symbol Vcc VI Vo Pd Topr Tstg Parameter Supply voltage Input voltage Output voltage Power dissipation Operating temperature Storage temperature Conditions With respect to GND Ta=25C Ratings -0.2 ~ 4.6 -0.2* ~ Vcc+0.2(max.4.6V) 0 ~ Vcc 1 -40 ~ 85 -65 ~150 Unit V V V W C C
* -1.0V in case of AC ( Pulse width 30ns )
DC ELECTRICAL CHARACTERISTICS Symbol VIH VIL VOH VOL II Io ICC1W ICC2W ICC1B ICC2B ICC3 ICC4 Parameter High-level input voltage Low-level input voltage High-level output voltage Low-level output voltage Input current Output current in off-state Word operation(16bit) Active supply current (AC,TTL level) Byte operation(8bit) Active supply current (AC,TTL level) Stand-by current
( Ta = - 40~85C, Vcc = 1.8V~2.7V, unless otherwise noted ) Conditions Limits Min 0.7 x Vcc -0.2* IOH = -0.1mA IOL = 0.1mA VI =0 ~Vcc BC1 and BC2 = VIH or S = VIH or OE = VIH, VI/O = 0~ Vcc BC1 and BC2 = VIL, S = VIL other inputs = VIH or VIL Output-open(duty 100%) 1.6 0.2 1 1 Min cycle 1MHz 15 7 10 5 25 10 15 8 4 2 0.3 Typ Max 0.4 Unit Vcc+0.2V V V V V A A mA mA mA mA A A mA
Min (BC1 = VIH and BC2 = VIL) or (BC1 = VIL and cycle BC2 = VIH) , S = VIL ,other inputs = VIH or VIL 1MHz Output-open(duty 100%) 1) SVcc-0.2V, other inputs = 0~Vcc 2) BC1 and BC2 Vcc-0.2V,S0.2V, other inputs = 0~Vcc BC1 and BC2 = VIH or S = VIH, other inputs = 0~Vcc -LI -HI
Stand-by current
* -1.0V in case of AC ( Pulse width 30ns )
CAPACITANCE Symbol CI CO
( Ta = - 40 ~85C, Vcc = 1.8V~2.7V, unless otherwise noted ) Parameter Conditions VI=GND, Vi=25mVrms, f=1MHz VO=GND, Vo=25mVrms, f=1MHz Min Limits Typ Max 6 10 Unit pF pF
Input capacitance Output capacitance
Note 1: Direction for current flowing into an IC is positive (no mark). Note 2: Typical value is Vcc = 2.0V, Ta = 25C Note 3: CI,CO are periodically sampled and are not 100% tested.
Aug.1. 1998
MITSUBISHI ELECTRIC
3
MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
AC ELECTRICAL CHARACTERISTICS ( Ta = - 40 ~85C, Vcc = 1.8V~2.7V, unless otherwise noted ) (1) MEASUREMENT CONDITIONS Input pulse level * * * * * * * VIH = 0.7 x Vcc + 0.2V, VIL = 0.2V 1 TTL Input rise and fall time * * * * 5ns Reference level * * * * * * * * VOH = 0.9V, VOL = 0.9V DQ Output loads * * * * * * * * * Fig.1,CL = 30pF CL = 5pF ( for ten, tdis ) Transition is measured 200mV from steady state voltage. ( for ten, tdis ) CL ( Including scope and JIG )
Fig.1 Output load (2)READ CYCLE Limits Symbol Parameter Read cycle time Address access time Chip select access time BC1 access time BC2 access time Output enable access time Output disable time after S high Output disable time after BC1 high Output disable time after BC2 high Output disable time after OE high Output enable time after S low Output enable time after BC1 low Output enable time after BC2 low Output enable time after OE low Data valid time after address change -10LI,-10HI Min Max 100 100 100 100 100 50 35 35 35 35 10 10 10 5 10 -12LI,-12HI Min Max 120 120 120 120 120 60 40 40 40 40 10 10 10 5 10 -15LI,-15HI Min Max 150 150 150 150 150 75 50 50 50 50 10 10 10 5 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCR ta(A) ta(S) ta(BC1) ta(BC2) ta(OE) tdis(S) tdis(BC1) tdis(BC2) tdis(OE) ten(S) ten(BC1) ten(BC2) ten(OE) tV(A)
(3)WRITE CYCLE Limits Symbol Parameter Write cycle time Write pulse width Address set up time Address set up time with respect to W BC1 setup time BC2 setup time Chip select set up time Data set up time Data hold time Write recovery time Output disable time after W low Output disable time after OE high Output enable time after W high Output enable time after OE low Output enable time after BC1 low Output enable time after BC2 low -10LI,-10HI Min Max 100 75 0 85 85 85 85 50 0 0 35 35 5 5 10 10 5 5 10 10 -12LI,-12HI Min Max 120 85 0 100 100 100 100 55 0 0 40 40 -15LI,-15HI Min Max 150 100 0 120 120 120 120 60 0 0 50 50 5 5 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCW tw(W) tsu(A) tsu(A-WH) tsu(BC1) tsu(BC2) tsu(S) tsu(D) th(D) trec(W) tdis(W) tdis(OE) ten(W) ten(OE) ten(BC1) ten(BC2)
Aug.1. 1998
MITSUBISHI ELECTRIC
4
MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
(4) TIMING DIAGRAMS Read cycle
tCR A 0~15 ta(A) ta(BC1) or ta(BC2)
(Note 4)
tv(A)
BC1 and/or BC2
tdis(BC1) or tdis(BC2) ta(S)
(Note 4)
S
(Note 4)
ta(OE) ten(OE)
tdis(S)
(Note 4)
OE
(Note 4)
ten(BC1) ten(BC2) ten(S)
tdis(OE)
DATA VALID
(Note 4)
DQ1~16
W = "H" level
Write cycle ( W control mode )
tCW A 0~15 tsu(BC1) or tsu(BC2) BC1 and/or BC2
(Note 4) (Note 4)
S
(Note 4)
tsu(S)
(Note 4)
tsu(A-WH) OE tsu(A) W tdis(W) tdis(OE)
DATA IN
tw(W)
trec(W) ten(OE) ten(W)
DQ1~16
STABLE
tsu(D)
Aug.1. 1998 MITSUBISHI ELECTRIC
th(D)
5
MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM Write cycle ( BC1, BC2 control mode )
tCW A 0~15 tsu(A) BC1 and/or BC2 tsu(BC1) or tsu(BC2) trec(W)
S
(Note 4) (Note 6) (Note 4)
W
(Note 4)
(Note 5) (Note 4)
tsu(D) DQ1~16
Write cycle (S control mode) DATA IN STABLE
th(D)
tCW A 0~15
BC1 and/or BC2
(Note 4) (Note 4)
tsu(A) S
(Note 6)
tsu(S)
trec(W)
W
(Note 4)
(Note 5) (Note 4)
tsu(D) DQ1~16
DATA IN STABLE
th(D)
Note 4: Hatching indicates the state is "don't care". Note 5: Writing is executed while S low overlaps BC1 and/or BC2 low and W low. Note 6: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or falling edge of S, the outputs are maintained in the high impedance state. Note 7:Don't apply inverted phase signal externally when DQ pin is output mode. Note 8:ten,tdis are periodically sampled and are not 100% tested. Note 9:tCR(Read cycle time) is defined as whole time from reading address set up to this address change under read mode set condition by S,W,OE,BC1 and/or BC2. Note 10:tCW(Write cycle time) is defined as whole time from writing address set up to this address change under write mode set condition by S,W,BC1 and/or BC2. Aug.1. 1998 MITSUBISHI ELECTRIC
6
MITSUBISHI LSIs
M5M51R16AWG -10LI, -12LI, -15LI, -10HI, -12HI, -15HI
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
POWER DOWN CHARACTERISTICS (1) ELECTRICAL CHARACTERISTICS Symbol Parameter ( Ta = - 40~85C, unless otherwise noted ) Test conditions Limits Typ
Min 1.0
Max
Unit V V
Vcc(PD) Power down supply voltage VI(S) Chip select input S Byte control inputs BC1 and BC2 1.8V Vcc(PD) 1.0V Vcc(PD) 1.8V 1.8V Vcc(PD) 1.0V Vcc(PD) 1.8V Vcc = 2.0V 1) S Vcc - 0.2V other inputs = 0~Vcc 2) BC1 and BC2 Vcc - 0.2V S 0.2V,other inputs = 0~Vcc -LI -HI
0.7 x Vcc Vcc(PD) 0.7 x Vcc Vcc(PD) 2 A 0.05 1 V
VI(BC)
ICC(PD)
Power down supply current
(2) TIMING REQUIREMENTS
( Ta = - 40 ~85C, unless otherwise noted ) Limits
Symbol
Parameter Power down set up time
Test conditions
Min 0 5
Typ
Max
Unit ns ms
tsu(PD)
trec(PD) Power down recovery time
(3) POWER DOWN CHARACTERISTICS S control mode
Vcc tsu(PD) 1.8V 1.8V trec(PD) 0.7 x Vcc S Vcc
0.7 x Vcc S
BC1 and BC2 control mode
Vcc tsu(PD) 1.8V 1.8V trec(PD) 0.7 x Vcc BC1 and BC2 Vcc
0.7 x Vcc BC1 and BC2
Aug.1. 1998
MITSUBISHI ELECTRIC
7

▲Up To Search▲

Price & Availability of M5M51R16AWG-10LI

	To Download M5M51R16AWG-10LI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .